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asix electronics corporation frist released date : sep/11/2000 2f, no.13, industry east rd. ii, science - based in dustrial park, hsin - chu city, taiwan, r.o.c. tel: 886 - 3 - 579 - 9500 fax: 886 - 3 - 579 - 9558 http://www.asix.com.tw ax88170 l usb to fast ethernet /homepna controller usb to fast ethernet /homepna controller document no.: ax170 - 12 / v1.2 / apr. 11 ?01 features single chip usb to 10/100mbps fast ethernet and 1/10mbps home pna network controller compliant with usb specification 1.0 and 1.1 full speed usb device with bus power capability usb communication class spec 1.0 compliant support 4 endpoint s on usb ieee 802.3u 100base - t, tx, and t4 compatible embedded 5k*16 bit sram support both full - duplex or half - duplex operation on fast ethernet provides a mii port for both et hernet and homepna phy interface supports suspended mode and remote wakeup (link_up or magic packet) optional phy power down mode for power saving provides optional mii/rmii interface with phy mode for multiple ports usb - to - usb bridge application. support 256/512 bytes serial eeprom (used for saving usb descriptors) support automatic loading of ethernet id, usb descriptors and adapter configuration from eeprom on power - on initialization external phy loop - back diagnostic capability small form factor 64 - pin lqfp package 48mhz and 2 5mhz operation, pure 3.3v operation with i/o 5v tolerance *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respect ive holders. product description the ax88170 usb to fast ethernet /homepna controller is a high performance and highly integrated controller with embedded 5k*16 bit sram. the ax88170 contains a usb interf ace to host cpu and compliant with usb standard v 1 .0 and v 1.1 . the interface between ax88170 and pc host is compliant with usb communication class spec ification 1.0. the ax88170 could be used for both 10m / 100mbps fast ethernet function based on ieee802.3 / ieee802.3u lan standard and 1m/10m homepna stand ard . the ax88170 supports media - independent interface (mii) or rmii (reduce mii) interface to simplify the design on implementing fast ethernet and homepna functions. the chip also provides an optional mii/rmii interface with phy mode, combine with etherne t repeater or switch ic can build a multiple ports usb - to - usb bridge application. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products info rmation. asix electronics reserves the rights to modify product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. ax88170 10/100 mbps ethernet phy/txrx magnetic rj45 usb i/f eeprom 1/10 mbps home lan phy magnetic rj11
asix electronics corporation 2 confidential ax88170 preliminary contents 1.0 in troduction ................................ ................................ ................................ ................................ ................................ ........... 4 1.1 g eneral d escription : ................................ ................................ ................................ ................................ ............................ 4 1.2 ax88170 b lock d iagram : ................................ ................................ ................................ ................................ ...................... 4 1.3 ax88170 p in c onnection d iagram with mii i nterface ................................ ................................ ........................... 5 1.4 ax88170 p in c onnection d iagram with rmii i nterface ................................ ................................ ......................... 6 2.0 signal descripti on ................................ ................................ ................................ ................................ ............................... 7 2.1 usb b us i nterface s ignals g roup ................................ ................................ ................................ ................................ .... 7 2.2 eeprom s ignals g roup ................................ ................................ ................................ ................................ ......................... 7 2.3 a mii interface signals gr oup (mac mode ) ................................ ................................ ................................ .................. 7 2.3 b mii interface signals gr oup (phy mode ) ................................ ................................ ................................ ..................... 8 2.4 rmii interface signal pin s (phy mode ) ................................ ................................ ................................ .......................... 9 2.5 m iscellaneous pins gr oup ................................ ................................ ................................ ................................ ................... 9 3.0 eeprom memory m apping ................................ ................................ ................................ ................................ ............... 11 4.0 usb commands ................................ ................................ ................................ ................................ ................................ ....... 12 4.1 usb standard commands ................................ ................................ ................................ ................................ ................... 12 4.2 usb c ommunication c lass c ommands ................................ ................................ ................................ ......................... 13 4.3 usb v endor c ommands ................................ ................................ ................................ ................................ ....................... 14 5.0 usb configurati on structure ................................ ................................ ................................ ................................ ... 16 5.1 usb c onfiguration . ................................ ................................ ................................ ................................ ............................. 16 5.2 usb i nterface c lass . ................................ ................................ ................................ ................................ ........................... 16 5.3 u sb e ndpoints . ................................ ................................ ................................ ................................ ................................ ....... 16 6.0 electrical spec ification and timing s ................................ ................................ ................................ ................. 17 6.1 a bsolute m aximum r atings ................................ ................................ ................................ ................................ ............ 17 6.2 g eneral o peration c onditions ................................ ................................ ................................ ................................ ...... 17 6.3 dc c haracteristics ................................ ................................ ................................ ................................ .............................. 17 6.4 a.c. t iming c haracteristics ................................ ................................ ................................ ................................ ............. 18 6.4.1 25m_xin ................................ ................................ ................................ ................................ ................................ ............ 18 6.4.2 48m_xin ................................ ................................ ................................ ................................ ................................ ............ 18 6.4.3 reset timing ................................ ................................ ................................ ................................ ................................ ...... 18 6.4.4 mii timing of mac mode ................................ ................................ ................................ ................................ ................ 20 6.4.5 mii timing of phy mode ................................ ................................ ................................ ................................ ................. 21 6.4.6 rmii interface timing of phy mode ................................ ................................ ................................ ............................. 22 6.4.7 station management timing ................................ ................................ ................................ .............................. 23 6.4.8 serial eeprom timing ................................ ................................ ................................ ................................ ............. 24 7.0 package informat ion ................................ ................................ ................................ ................................ ....................... 25 appendix a: system a pplications ................................ ................................ ................................ ................................ .... 26 a.1 usb to f ast e thernet c onverter ................................ ................................ ................................ ................................ 26 a.2 usb to f ast e thernet and / or h ome lan c ombo solution ................................ ................................ ................ 27 a.3 usb - to - usb or usb - to - e thernet b ridge through e thernet r epeater c ontroller ............................ 28 a.4 usb - to - usb or usb - to - e thernet b ridge through e th ernet s witch c ontroller ................................ . 28 demonstration circui t a: ax88170 + ethe rnet phy ................................ ................................ ............................. 29 demonstration circui t b: ax88170 + home pna 1m8 phy ................................ ................................ .................... 31 demonstration circui t c: 4 usb ports + 1 ethernet port bridge ap ................................ ..................... 33
asix electronics corporation 3 confidential ax88170 preliminary figures f ig - 1 ax88170 b lock d iagram ................................ ................................ ................................ ................................ ..................... 4 f ig - 2 ax88170 p in c onnection d iagram with mii i nterface ................................ ................................ ......................... 5 f ig - 3 ax88170 p in c onnection d iagram rmii i nterface ................................ ................................ ................................ .. 6 tables t ab - 1 usb bus interface signal s group ................................ ................................ ................................ ................................ .. 7 t ab - 2 eeprom bus interface signal s group ................................ ................................ ................................ ......................... 7 t ab - 3 mii interface signals gr oup (mac mode ) ................................ ................................ ................................ ................. 8 t ab - 4 mii interface signals gr oup (phy mode ) ................................ ................................ ................................ ................... 8 t ab - 5 rmii interface signal pin s (phy mode ) ................................ ................................ ................................ ....................... 9 t ab - 6 m iscellane ous pins group ................................ ................................ ................................ ................................ ............. 10 t ab - 7 eeprom m emory m apping ................................ ................................ ................................ ................................ ............. 11
asix electronics corporation 4 confidential ax88170 preliminary 1.0 introduction 1.1 general description: the ax88170 usb to fast ethernet controller is a high performance and highly integrated usb bus ethernet controller with embedded 5k* 16 bit sram. the ax88170 contains a full speed usb interf ace to host cpu and compliant with usb communication class spec. 1.0 . the ax88170 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee80 2.3u lan standard. the ax88170 supports media - independent interface (mii) or rmii (reduce mii) interface to simplify the design on implementing fast ethernet and homepna functions. the chip also provides an optional mii/rmii interface with phy mode, combin es with ethernet repeater or switch ic can build a multiple ports usb - to - usb bridge application. ax88170 use s 64 - pin lqfp low profile package, 48mhz operation for usb and 2 5mhz o peration for ethernet , cmos process with pure 3.3v operation and 5 volt i/o t olerance. 1.2 ax88170 block diagram: fig ? 1 ax88170 block diagram mac core memory arbiter usb to ethernet bridge usb core and interface sta seeprom loader i/f d - /d+ m ii i/f or rmii i/f smdc smdio eecs eeck eedi eedo 5k* 16 sram
asix electronics corporation 5 confidential ax88170 preliminary 1.3 ax88170 pin connection diagram with mii interface the ax88170 is housed in the 64 - pin plastic light quad flat pack. see fig ? 2 ax88170 pin connection diagram . fig ? 2 ax88170 pin connection diagram with mii interface 1 5 6 4 7 2 3 8 9 10 11 12 13 14 15 16 30 29 28 24 23 25 27 26 asix 22 18 17 19 31 21 20 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 64 63 61 62 60 59 58 57 56 55 54 50 49 col test0 vss vdd /rst vss vdd vss vdd vdd vss rxd0 rxd1 rxd2 rxd3 rx_er rx_dv txd0 txd1 txd2 txd3 crs tx_clk 25m_xin vss vdd 52 53 51 vss vss d+ /s_rmii /s_mac /s_fdpx spd_up eecs ax88170 rx_clk tx_en test1 test2 d- mdc mdio /phy_rst 25m_clko 25m_xout 48m_xin 48m_xout eeck eedi eedo vss vdd vdd vdd vss test3 ld_rdy test_out vdd s_ext act/link test4 (mii interface) gpio0 gpio1 /homelink
asix electronics corporation 6 confidential ax88170 preliminary 1.4 ax88170 pin connection diagram with r mii interface the ax88170 is housed in the 64 - pin plastic light quad flat pack. see fig ? 3 ax88170 pi n connection diagram rmii interface . fig ? 3 ax88170 pi n connection diagram rmii interface 1 5 6 4 7 2 3 8 9 10 11 12 13 14 15 16 30 29 28 24 23 25 27 26 asix 22 18 17 19 31 21 20 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 64 63 61 62 60 59 58 57 56 55 54 50 49 col test0 vss vdd /rst vss vdd vss vdd vdd vss rxd0 rxd1 nc nc nc nc txd0 txd1 nc nc crs_dv ref_clk 25m_xin vss vdd 52 53 51 vss vss d+ /s_rmii /s_mac /s_fdpx spd_up eecs ax88170 nc tx_en test1 test2 d- mdc mdio /phy_rst 25m_clko 25m_xout 48m_xin 48m_xout eeck eedi eedo vss vdd vdd vdd vss test3 ld_rdy test_out vdd s_ext act/link test4 (rmii interface) gpio0 gpio1 /homelink
asix electronics corporation 7 confidential ax88170 preliminary 2.0 signal description the following terms describe the ax88170 pin - out: all pin names with the ?/? suffix are asserted low. the following abbreviations are used in following tables . i input pu pull up o output p d pull down i/o input/output p power pin od open drain 2.1 usb bus i nterface s ignals g roup signal type pin no. description d+ i/o 1 usb data plus pin d - i/o 2 usb data minus pin tab ? 1 usb b us interface signals gr oup 2.2 eeprom s ignals g roup signal type pin no. description eecs o 45 eeprom chip select : eeprom chip select signal. eeck o 46 eeprom clock : signal connected to eeprom clock pin. eedi o 47 eeprom data in : signal connected to eeprom data input pin. eedo i /pu 48 eeprom data out : signal connected to eeprom data output pin. tab ? 2 eeprom bus interface signals group 2.3a mii interface signals group (mac mode) when /s_rmii=1 and /s_mac=0 signal type pin no. description rxd[3 :0] i/pu 29, 28 27, 26 receive data: rxd[3:0] is driven by the phy synchronously with respect to rx_clk. crs i/pd 15 carrier sense: asynchronous signal crs is asserted by the phy when either the transmit or receive medium is non - idle. rx_dv i/pd 32 rece ive data valid: rx_dv is driven by the phy synchronously with respect to rx_clk. asserted high when valid data is present on rxd [3:0]. rx_er i/pd 31 receive error: rx_er is driven by phy and synchronous to rx_clk, is asserted for one or more rx_clk per iods to indicate to the port that an error has detected. rx_clk i/pu 24 receive clock: rx_clk is a continuous clock that provides the timing reference for the transfer of the rx_dv,rxd[3:0] and rx_er signals from the phy to the mii port of the mac. col i /pd 13 collision: this signal is driven by phy when collision is detected. tx_en o 22 transmit enable: tx_en is transition synchronously with respect to the rising edge of tx_clk. tx_en indicates that the port is presenting
asix electronics corporation 8 confidential ax88170 preliminary signal type pin no. description nibbles on txd [3:0] for trans mission. txd[3:0] o 21, 20 19, 18 transmit data: txd[3:0] is transition synchronously with respect to the rising edge of tx_clk. for each tx_clk period in which tx_en is asserted ,txd[3:0] are accepted for transmission by the phy. tx_clk i 16 transmit cl ock: tx_clk is a continuous clock from phy. it provides the timing reference for the transfer of the tx_en and txd[3:0] signals from the mii port to the phy. mdc o 12 station management data clock: the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. mdc is a 2.5mhz frequency clock output. mdio i/o/pu 14 station management data input/output: serial data input/output transfers from/to the phys. the transfer protocol conforms to the ieee 802.3u mii spe cification. tab ? 3 mii interface signals group (mac mode) 2.3b mii interface signals group (phy mode) when /s_rmii=1 and /s_mac=1 signal type pin no. description rxd[3:0] o 29, 28 27, 26 receive data: basically rxd[3:0] is tran sformed from txd[3:0] of mac mode of mii interface. crs o 15 carrier sense: basically crs is transformed from tx_en of mac mode of mii interface. rx_dv o 32 receive data valid: basically rx_dv is transformed from tx_en of mac mode of mii interface. rx_er o 31 receive error: no used rx_clk o 24 receive clock: basically rx_clk is sourced from internal 25mhz local clock. col o 13 collision: this signal is generated by internal logic when collision is detected. tx_en i/pd 22 transmit enable: basical ly tx_en is simulation from rx_dv of mac mode of mii interface. txd[3:0] i/pu 21, 20 19, 18 transmit data: basically txd[3:0] is simulation from rxd[3:0] of mac mode of mii interface. tx_clk o 16 transmit clock: basically tx_clk is sourced from inter nal 25mhz local clock. tab ? 4 mii interface signals group (phy mode)
asix electronics corporation 9 confidential ax88170 preliminary 2.4 rmii interface signal pins (phy mode) when /s_rmii=0 and /s_mac=1 signal type pin no. description rxd[1:0] o 27, 26 receive data : basically rxd[1:0] is transformed from txd[1:0] of mac mode of rmii interface. crs_dv o 15 carrier sense _ data valid : basically crs_dv is transformed of tx_en from mac mode of rmii interface. txd[1:0] i/pu 19, 18 transmit data : basically txd[1:0] is transformed from rx d[1:0] of mac mode of rmii interface. tx_en i/pd 22 transmit enable : basically tx_en is transformed from rx_dv from mac mode of rmii interface. ref_clk i 16 reference clock : the input is a continue clock at 50mhz for timing reference with rmii interf ace. tab ? 5 rmii interface signal pins (phy mode) 2.5 miscellaneous pins group signal type pin no. description 25m_xin i 35 cmos local clock : typical a 25mhz clock, +/ - 100 ppm, 40% - 60% duty cycle. ( see application note also ) crystal oscillator input : typical a 25mhz crystal, +/ - 25 ppm can be connected across 25m_xin and 25m_xout. 25m_xout o 36 crystal oscillator output : typical a 25mhz crystal, +/ - 25 ppm can be connected across 25m_xin and 25m_xout. if a single - ended ex ternal clock is connected to 25m_xin, the crystal output pin should be left floating. 48m_xin i 52 48mhz cmos clock in : typical a 48mhz clock, +/ - 500 ppm, 40% - 60% duty cycle. ( see application note also ) 48mhz crystal oscillator input: typical a 48mhz crystal, +/ - 100 ppm can be connected across 48m_xin and 48m_xout. 48m_xout o 51 48mhz crystal oscillator output: typical a 48mhz crystal, +/ - 100 ppm can be connected across 48m_xin and 48m_xout. if a single - ended external clock is connected to 48m_xin, the crystal output pin should be left floating. 25m_clko o 33 clock output : this clock is source from 25m_xin. / rst i /pd 4 reset : reset is active low then place ax88170 into reset mode immediately. during ris ing edge the ax88170 loads the eeprom data. /s_rmii i/pu 43 set to rmii mode: 0: rmii mode is selected. 1: mii mode is selected. (default) /s_mac i/pd 9 set mii/rmii interface to mac mode: 0: mac mode is selected. (default) 1: phy mode is selected. /s_fdpx i/pd 8 set duplex mode when phy mode is selected or when s_ext is set and mac mode is selected: 0: full - duplex mode is selected. (default) 1: half - duplex mode is selected. s_ext i/pd 7 select where duplex mode is sourced from when mac mode: 0: duplex mode depands on internal register. (default ) 1: duplex mode depands on external signal /s_fdpx spd_up id 6 the setting is enable speed up test mode:
asix electronics corporation 10 confidential ax88170 preliminary 0: normal operation mode. 1: speed up test mode enable. test0 i/pd 55 test pin: this pin for test purpose only. pull down the pin or keep no connec tion for normal operation. test1 i/pd 56 test pin: this pin for test purpose only. pull down the pin or keep no connection for normal operation. test2 i 57 test pin: this pin for test purpose only. pull down the pin for normal operation. test3 i/pd 58 t est pin: this pin for test purpose only. pull down the pin or keep no connection for normal operation. test4 i/pd 61 test pin: this pin for test purpose only. pull down the pin or keep no connection for normal operation. test_out o 60 test output pin: th is pin for test purpose only. ldrdy o 62 load eeprom data completed indicator. active high. act/link o 63 led indicator: when link fail, drives logic high always. when link ok, the pin drives logic low and will drives high a period when line has activity (data transfer). /phy_rst o 39 phy reset: this pin is used to reset phy and is an active low signal. gpio0 b/pd 38 general purpose i/o 0: refer to section 4.3 usb vendor commands gpio1 b/pd 40 general purpose i/o 1: refer to section 4.3 usb vendor comm ands /homelink i/pu 41 link status: for external homephy link state input active low vdd p 3, 10, 23, 30 37, 44, 50 54,59 power supply: +3.3v dc. vss p 5, 11 17, 25, 34 42, 49, 53 64 power supply: +0v dc or ground power. tab - 6 miscel laneous pins group mii/rmii interface cross reference table mii rmii rxd[0] rxd[0] rxd[1] rxd[1] rxd[2] rxd[3] crs crs_dv rx_dv rx_clk rx_er tx_en tx_en tx_clk ref_clk (50mhz) txd[0] txd[0] txd[1] txd[1] txd[2] txd[3] col
asix electronics corporation 11 confidential ax88170 preliminary 3.0 eeprom memory mapping eeprom offset high byte low byte 00h reserved word count for preload 01h * flag 02h length of device des criptor (byte) eeprom offset of device descriptor 03h length of configurat ion descriptor (byte) eeprom offset of con figuration descriptor 04h node id 1 node id 0 05h node id 3 node id 2 06h node id 5 node id 4 07h language id high byt e language id low byte 08h length of string ind ex 1 eeprom offset of string index 1 09h length of string ind ex 2 eeprom offset of st ring index 2 0ah length of string ind ex 3 eeprom offset of string index 3 0bh length of string ind ex 4 eeprom offset of string index 4 0ch length of string ind ex 5 eeprom offset of string index 5 0dh length of string ind ex 6 eeprom offset of string ind ex 6 0eh length of string ind ex 7 eeprom offset of string index 7 0fh length of string ind ex 8 eeprom offset of string index 8 (19h) 10h max packetsize high byte max packet low byte 11h homepna phy id ethernet phy id 12h pause packet high wa ter level pause packet low wat er level 13h - 18h reserved 19h 03h 0ch 1ah byte 2 of unicode mac address ** byte 1 of unicode mac address 1bh byte 4 of unicode mac address byte 3 of unicode mac address 1ch byte 6 of unicode mac address byte 5 of unicode mac address 1dh byte 8 of unicode mac address byte 7 of unicode mac address 1eh byte 10 of unicode mac address byte 9 of unicode mac address 1fh byte 12 of unicode mac address byte 11 of unicode mac address 20h - 4fh device /configuration /interface / endpoint descr iptor 50h - ffh strings tab - 7 eeprom memory mapping note: * flag: bit 0 self powere d (for usb getstatus) bit 1 bus powered ( reserved ) bit 2 remote wakeup (for usb getstatus) bit 3 interrupt endpoint enaable ( reserved ) bit 4 clknostop (for self power only) bit 5 reserved bit 6 reserved bit 7 reserved bit 8 capture effective mode bit 9 flow control selector (1: software, o: read from phy) bit a ? f reserved bit 4 also effect led display, if high then led display usb active only otherwise display usb link and activity. (in self power mode bit_4 set to high) **unicode mac address: if the mac?s no de id is 01,23,45,67,89,abh respect to node id 0, node id 1, ? node id5 then the unicode will be 30 - 31,32 - 33,34 - 35,36 - 37,38 - 39,41 - 42h respects to byte 1 of unicode mac address - byte 2 of unicode mac address, ? - byte 12 of unicode mac address.
asix electronics corporation 12 confidential ax88170 preliminary 4.0 usb commands the re are three command groups for endpoint 0 in ax88170: l the usb standard commands l usb communication class commands l usb vendor commands. 4.1 usb standard commands ** the language id is 0x0904 for english ** ppll means buffer length ** cc means configuration number ** i i means interface number setup command data in/out description 80 06 00 01 00 00 ll pp data ppll bytes get device descriptor 80 06 00 02 00 00 ll pp data ppll bytes get configuration descriptor 80 06 00 03 00 00 ll pp data 2 bytes get supported language id 80 06 01 03 09 04 ll pp data ppll bytes get manufacture string 80 06 02 03 09 04 ll pp data ppll bytes get product string 80 06 03 03 09 04 ll pp data ppll bytes get serial number string 80 06 04 03 09 04 ll pp data ppll bytes get configuration string 80 06 05 03 09 04 ll pp data ppll bytes get interface 0 string 80 06 06 03 09 04 ll pp data ppll bytes get interface 1/0 string 80 06 07 03 09 04 ll pp data ppll bytes get interface 1/1 stirng 80 06 08 03 09 04 ll pp data 12 bytes get ethernet address string 80 08 00 00 00 00 01 00 data 1 bytes get configuration 00 09 cc 00 00 00 00 00 no data set configuration 81 0a 00 00 i i 00 01 00 data 1 byte get interface 01 0b as 00 01 00 00 00 no dat a set interface
asix electronics corporation 13 confidential ax88170 preliminary 4.2 usb communication class commands ** nn: number of multicast addresses ** bbaa: ethernet packet filter ** ttss: number of ethernet statics setup command data in/out description 21 40 nn 00 00 00 6*n 00 data 6*n bytes set ethern et multicast filters 21 41 00 00 00 00 10 00 data 16 bytes set ethernet power management pattern a1 42 00 00 00 00 02 00 data 2 bytes get ethernet power management pattern 21 43 aa bb 00 00 00 00 no data set ethernet packet filter (aa bb) descripti on of ethernet packet filter (aa bb) bitmap bb = [d15:d8] aa = [d7:d0] bit position description d15..d5 reserved (reset to zero) d4 packet_type_multicast 1: all multicast packets enumerated in the device ? s multicast address list are forwarded u p to the host. 0: disabled. d3 packet_type_broadcast 1: all broadcast packet packets received by the networking device are forwarded up to the host. 0: disable. d2 packet_type_directed 1: directed packets received containing a destination a ddress equal to the mac address of the networking device are forwarded up to the host. 0: always not set to zero. d1 packet_type_all_multicast 1 : all multicast frames received by the networking device are forwarded up to the host, not just the ones enumerated in the device ? s multicast address list. 0: disabled. d0 packet_type_promiscuous 1: all frames received by the networking device are forwarded up to the host. 0: disabled. tab - 9 ethernet packet filter bitmap
asix electronics corporation 14 confidential ax88170 preliminary 4.3 us b vendor commands setup command data in/out description c0 02 xx yy 00 0m 02 00 data 2 bytes read rx/tx sram m = 0 : rx, m=1 : tx 40 03 xx yy pp qq 00 00 no data write rx sram 40 04 xx yy pp qq 00 00 no data write tx sram 40 06 00 00 00 00 00 00 no data disable h/w mii operation c0 07 pi 00 rg 00 02 00 data 2 bytes read mii register 40 08 pi 00 rg 00 02 00 data 2 bytes write mii register c0 09 00 00 00 00 01 00 data 1 bytes read mii operation mode 40 0a 00 00 00 00 00 00 no data enable h/w mii operation c0 0b dr 00 00 00 02 00 data 2 bytes read srom 40 0c dr 00 mm ss 00 00 no data write srom 40 0d 00 00 00 00 00 00 no data write srom enable 40 0e 00 00 00 00 00 00 no data write srom disable c0 0f 00 00 00 00 02 00 data 2 bytes read rx cont rol register 40 10 rr 00 00 00 00 00 no data write rx control register c0 11 00 00 00 00 03 00 data 3 bytes read ipg/ipg1/ipg2 register 40 12 ii 00 00 00 00 00 no data write ipg register 40 13 ii 00 00 00 00 00 no data write ipg1 register 40 14 ii 0 0 00 00 00 00 no data write ipg2 register c0 15 00 00 00 00 08 00 data 8 bytes read multi - filter array 40 16 00 00 00 00 08 00 data 8 bytes write multi - filter array c0 17 00 00 00 00 06 00 data 6 bytes read node id c0 19 00 00 00 00 02 00 data 2 byte s read ethernet/homepna phyid c0 1a 00 00 00 00 01 00 data 1 byte read medium status (*) 40 1b mm 00 00 00 00 00 no data write medium mode (*) c0 1c 00 00 00 00 01 00 data 1 byte get monitor mode status (**) 40 1d mm 00 00 00 00 00 no data set monitor m ode on/off (**) notes: * read / write medium status bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 read gpi1 x gpi0 x home_link 100mhz full_duplex link w rite gpo1 gpo1en gpo0 gpo0en frbi 100mhz full_duplex link ** read / write monitor mode bit7 - 5 bit4 bit 3 bit2 bit1 bit0 read reserved (hardware_version for asix only) flow_contron_en x magic_packet_en link_up_wake monitor_mode write x flow_contron_en x magic_packet_en link_up_wake monitor_mode
asix electronics corporation 15 confidential ax88170 preliminary interrupt endpoint report link status format byte numbe r byte 0 a1 fixed value byte 1 00 fixed value byte 2 nn bit_0 : ethernet link state, bit_1 : home phy link state (active high) byte 3 00 fixed value byte 4 nn bit_0 : 100mhz speed detect byte 5 nn reserved ( hardware version for asix only) byte 6 n n bit_0 : full duplex byte 7 00 fixed value
asix electronics corporation 16 confidential ax88170 preliminary 5.0 usb configuratio n structure 5.1 usb configuration. the ax88170 supports 1 configuration only. 5.2 usb interface class . the ax88170 support s 2 interfaces, the interface 0 is data interface and inte rface 1 is for communication interface. 5.3 usb endpoints. the ax88170 supports 4 endpoints. endpoint 0 control endpoint, it is for configuring device. endpoint 1 (optional) interrupt endpoint, it is for reporting status change endpoint 2 bulk out endpoint, it is for transmitting ethernet packet. endpoint 3 bulk in endpoint, it is for receiving ethernet packet.
asix electronics corporation 17 confidential ax88170 preliminary 6.0 electrical specification and timings 6.1 absolute maximum ratings description sym min max units operating temperature ta 0 +8 5 c storage temperature ts - 55 +150 c supply voltage vdd - 0.3 +3.6 v input voltage vin - 0.3 vdd+0.3 v output voltage vout - 0.3 vdd+0.3 v lead temperature (soldering 10 seconds maximum) tl - 55 +240 c note: stress above those listed under absolute m aximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability. 6.2 general operation conditions description sym min tpy max units operating temper ature ta 0 25 +70 c supply voltage vdd +3.0 +3.30 +3.6 v 6.3 dc characteristics (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 70 c) description sym min tpy max units low input voltage vil - 0.3*vdd v high input voltage vih 0.7*vdd - v low output voltage v ol - 0.4 v high output voltage voh 2.4 - v input leakage current iil - 1 +1 ua output leakage current iol - 10 +10 ua input pull - up / down resistance ri 75 k ohm description sym min tpy max units power consumption (3.3v) spt3v 40 ma
asix electronics corporation 18 confidential ax88170 preliminary 6.4 a .c. timing characteristics 6.4.1 25m_xin 25m_xin tr tf tlow 25m_clko tod symbol description min typ. max units t cyc cycle time 40 ns t high clk high time 16 20 24 ns t low clk low time 16 20 24 ns t r/ t f clk slew rate 1 - 4 ns tod lclk/xtalin to 25m_c lko out delay 8 29 ns 6.4.2 48m_xin 48m_xin tr tf tlow symbol description min typ. max units t cyc cycle time 20.83 ns t high clk high time 8.3 10.42 12.5 ns t low clk low time 8.3 10.42 12.5 ns t r/ t f clk slew rate 1 - 4 ns 6.4.3 reset timing 25m_xin /rst symbol description min typ. max units trst reset pulse width 100 - - 25m _xin tcyc thigh tcyc thigh
asix electronics corporation 19 confidential ax88170 preliminary
asix electronics corporation 20 confidential ax88170 preliminary 6.4.4 mii timing of mac mode ttclk ttch ttcl txclk(in) ttv tt h txd<3:0>(out) txen(out) trclk trch trcl rxclk(in) trs trh rxd<3:0>(in) rxdv(in) trs1 rxer(in) crs(in) symbol description min typ. max units ttclk cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns ttv clock to data valid - - 20 ns tth data output hold time 5 - - ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 n s trcl low time(10mbps) 140 - 260 ns trs data setup time 6 - - ns trh data hold time 10 - - ns trs1 rxer data setup time 10 - - ns
asix electronics corporation 21 confidential ax88170 preliminary 6.4.5 mii timing of phy mode ttclk ttch ttcl txclk(out) tts tth txd<3:0>(in) txen(in) trclk trch trcl rxclk(out) trs trh rxd<3:0>(out) rxdv(out) tcrsh crs(out) symbol descri ption min typ. max units ttclk cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns tts txd, txe n setup to txclk high 15 - - ns tth txd, txen hold to txclk high 0 - - ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 n s trcl low time(10mbps) 140 - 260 ns trv rxd, rxdv valid to rxclk high 10 - - ns trh rxclk high to rxd, rxdv invalid 10 - - ns tcrsh rxclk high to crs invalid 10 - - ns
asix electronics corporation 22 confidential ax88170 preliminary 6.4.6 rmii interface timing of phy mode tclk tch tcl ref_clk ts th tx_en (in) txd (in) crs_dv (out) tod tod rxd (out) symbol description min typ. max units tclk ref_clk clock cycle time 19.998 20 20.002 ns tch ref_clk clock high time 7 10 13 ns tcl ref_clk clock low time 7 10 13 ns ts txen and txd data setup to ref_clk high 4 ns th txen and txd data hold from ref_clk high 2 ns tod ref_clk rising edge to crs_dv, rxd delay 4 ns
asix electronics corporation 23 confidential ax88170 preliminary 6.4.7 station management timing mdc mdio (output) mdio (input) symbol description min typ. max units tclk mdc clock cycle time 2560 ns tch mdc clock hig h time 1280 ns tcl mdc clock low time 1280 ns tod clock falling edge to output valid delay 2 9 ns ts data in setup time 10 ns th data in hold time 100 ns to d tclk ts th tch tcl
asix electronics corporation 24 confidential ax88170 preliminary 6.4.8 serial eeprom timing eeck ee di (output) eecs eedo (input) symbol description min typ. max units tclk eeck clock cycle time 5120 ns tch eeck clock high time 2500 9 ns tcl eeck clock low time 2500 9 ns tdv eedi data valid output to eeck high time 500 ns tod eeck high to eedi data output delay time 500 ns tscs eecs valid to eeck high time 300 ns thcs eeck low to eecs invalid time 0 ns tlcs minimum eecs low time 2500 ns ts data input setup time 10 ns th data input hold time 100 ns tch tclk tcl valid valid tdv tod tsc s thcs tlcs th data va lid ts
asix electronics corporation 25 confidential ax88170 preliminary 7.0 package information b e d hd e he pin 1 a2 a1 l l1 q a
asix electronics corporation 26 confidential ax88170 preliminary milimeter symbol min. nom max a1 0.05 0.1 0.15 a2 1.35 1.40 1.45 a 1.60 b 0.17 0.22 0.27 d 10.00 e 10.00 e 0.5 hd 12.00 he 12.00 l 0.45 0.60 0.75 l1 1 .00 q 0 3.5 7 appendix a: system applications some typical applications for ax88170 are illustrated bellow. a.1 usb to fast ethernet converter ax88170 10/100 phy/txrx magnetic rj45 usb i/f eeprom
asix electronics corporation 27 confidential ax88170 preliminary a.2 usb to fast ethernet and/or homelan combo solution ax88170 10/100 mbps ethernet phy/txrx magnetic rj45 usb i/f eeprom 1/10 mbps home lan phy magnetic rj11
asix electronics corporation 28 confidential ax88170 preliminary a.3 usb - to - usb or usb - to - ethernet bridge through ethernet repeater controller note : using ax88871 for 8 - port or less then 8 - port solutions. a.4 usb - to - usb or usb - to - et hernet bridge through ethernet switch controller ax88875 repeater controller ax88170 ethernet phy for up - link ax88170 ax88170 ax88170 client pc a client pc b client pc c client pc d mii i/f mii i/f mii i/f mii i/f mii i/f to ethernet backend usb i/f usb i/f usb i/f usb i/f ax88615 switch controller ax88170 ethernet phy for up - link ax88170 ax88170 ax88170 client pc a client pc b client pc c client pc d mii i/f mii i /f mii i/f mii i/f mii i/f to ethernet backend usb i/f usb i/f usb i/f usb i/f
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 29 demonstration circuit a: ax88170 + ethernet phy txd1 r6 18 l2 fuse act/link# col eedi l4 f.b. vdd3 rst# d- vdd3 c1 8p c13 0.1u r1 20k y2 25m 1 2 4 3 j1 usb-con 1 2 3 4 gnd vdd5 d+ d- s s c6 20p *1 usb port link/act led 25mhz rxd2 eedi eecs txd0 ax88710 l application for 10base-t/100base-tx crs r5 1.5k c14 0.47u txen rxdv rxd0 c5 22p u1 ax88170 l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d+ d- vdd /rst vss spd_up s_ext /s_fdpx /s_mac vdd vss mdc col mdio crs tx_clk vss txd0 txd1 txd2 txd3 tx_en vdd rx_clk vss rxd0 rxd1 rxd2 rxd3 vdd rx_er rx_dv 25m_clko vss 25m_xin 25m_xout vdd gpio0 /phy_rst gpio1 /homelink vss /s_rmii vdd eecs eeck eedi eedo vss vdd 48m_xout 48m_xin vss vdd test0 test1 test2 /ep78dis test3 vdd test_out test4 leerdy act/link vss c11 0.1u txen vdd3 r8 4.7k prst# rxclk c9 0.1u *2 rc reset (option) txd3 gnd rxd3 c4 20p rxclk mdc u3 93c56r 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc r3 0 mdio rxer c17 0.1u + c15 10u/16v 25mhz 25m_xout u4 ams1117 - 3.3 3 2 1 vin vout adj/gnd rst# rxd0 gnd c12 0.1u r4 330 txd1 eedo d1 led vdd3 vdd3 25m_xin vdd3 d+ c3 20p c7 20p eeck prst# 48m_xout 25m_xout txd2 rxd1 gnd vdd3 c19 1000p 48m_xin 170ap1a.sch 2.0 ax88170 asix electronic corporation b 1 2 monday, february 26, 2001 title size document number rev date: sheet of r2 1m l1 2.2uh rxdv rxd2 y1 48m vdd3 r9 10k txd0 vdd3 mdio 48m_xout vdd3 d2 1n4148 eedo eecs + c16 10u/16v txd2 txd3 r7 18 l3 f.b. mdc rxd1 eeck txclk c18 0.01u vdd3 vdd3 vdd3 c2 8p c10 0.1u c8 0.01u 48m_xin col rxer 25m_xin rst# crs rxd3 5v u2 v6300c 1 2 3 vcc reset# gnd txclk
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 30 tdp gnd c40 0.1u l5 f.b. c30 0.1u vdd3 c27 0.1u activity led spdled mdio txd0 r15 4.7k txen d4 led rx- r19 75 r35 510 r16 49.9 vdd3 r32 510 rxdv r25 2k txd3 c23 0.01u tdn 25mhz r20 75 vdd3 rxer j2 rj45 2 1 3 6 4 5 7 8 s s r21 75 r17 49.9 crs tx+ r18 75 r31 4.7k vdd3 l6 f.b. vdd3 r24 4.7k r28 4.65k vdd3 gnd gnd r12 4.7k r26 4.7k gnd c35 0.1u d6 led full duplex led tx- d3 led r23 4.7k + c37 4.7u/16v fulled vdd3 c26 1000p c39 0.1u c33 0.1u vdd3 c34 0.1u rxd1 gnd gnd d5 led rxd3 vdd3 c42 0.1u r11 49.9 txclk gnd c22 0.01u/2kv prst# vdd3 c29 1000p r34 510 col c20 0.01u r33 510 link led actled rxd2 + c25 4.7u/16v gnd rxd0 actled c31 0.1u rx+ fulled vdd3 u5 lu3x31t-t64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 resv 100fden gnd9 autonen tptxtr eqgnd1 eqvdd1 resv rstz phy[0] 100hden phy[1] vdd5 gnd1 vdd1 mdiointz/phy[2] ledsp/10fden rxdv rxer rxd3 rxd2 rxd1 rxd0 rxclk vdd8 gnd8 txen txer txd3 txd2 txd1 txd0 rxvdd2 rxgnd2 tprx- tprx+ rxgnd1 rxvdd1 csvdd csvdd csgnd txvdd2 tptx- tptx+ txgnd1 txvdd1 ref100 ref10 xout xin xtlvdd mdc lnkled/bpalign ledfd/10hden ledcol/bp4b5b ledtx/actled/bpscr ledrx col/phy[4] vdd6 vdd4 gnd4 mdio crs/phy[3] txclk r10 49.9 vdd3 c24 0.01u c32 0.1u r13 4.7k r22 4.7k rdn + c41 4.7u/16v c36 0.1u lnkled vdd3 rxclk set phy address to 00010 ?g spdled r14 4.7k u6 ts6121a 1 2 3 6 7 8 9 10 11 14 15 16 1 2 3 6 7 8 9 10 11 14 15 16 r27 301 c21 0.01u + c28 4.7u/16v r29 1 lnkled vdd3 speed led 170ap1a1.sch 2.0 lu3x31 asix electronic corporation b 2 2 monday, february 26, 2001 title size document number rev date: sheet of txd2 txd1 vdd3 r30 4.7k c38 1000p rdp mdc tx 1:1 rx 1:1
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 31 demonstration circuit b: ax88170 + homepna 1m8 phy col vdd3 r19 1m c32 0.01u 48m_xout 25mhz c31 0.1u txd1 prst# c20 20p r29 10k c28 0.47u eecs eedi 25m_xin rxd3 r22 1.5k c23 0.1u crs r21 330 vdd3 rxdv c15 8p u6 ams1117 3 2 1 vin vout adj/gnd c22 0.01u vdd3 eeck d- + c29 47u/16v c18 20p rxd1 txd2 c25 0.1u r25 18 gnd r27 4.7k gnd prst# c33 1000p 1 2 4 3 j2 usb-con 1 2 3 4 gnd vdd5 d+ d- s s eecs vdd3 rxd3 c17 20p l4 f.b. rxdv rxd0 48m_xout u4 v6300c 1 2 3 vcc reset# gnd mdio vdd3 vdd3 25m_xout eedi vdd3 d+ u3 ax88170 l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d+ d- vdd /rst vss spd_up s_ext /s_fdpx /s_mac vdd vss mdc col mdio crs tx_clk vss txd0 txd1 txd2 txd3 tx_en vdd rx_clk vss rxd0 rxd1 rxd2 rxd3 vdd rx_er rx_dv 25m_clko vss 25m_xin 25m_xout vdd phy_rst /phy_rst phy_pwn /phy_pwn vss /s_rmii vdd eecs eeck eedi eedo vss vdd 48m_xout 48m_xin vss vdd test0 test1 test2 /ep78dis test3 vdd test_out test4 leerdy act/link vss u5 93c56r 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc txclk col rxclk c27 0.1u 48m_xin 25m_xout rst# *2 rc reset (option) + c30 47u/16v l3 2.2uh act/link# *1 usb port link/act led vdd3 txen l5 f.b. eedo gnd rxd1 mdio c16 8p mdc vdd3 y2 25m c24 0.1u c19 22pf r26 4.7k txd3 y1 48m c26 0.1u r18 20k 5v txclk r24 18 ax88710 application for 1m8 homepna eeck rst# txen vdd3 25m_xin r20 0 25mhz rxd0 txd1 rxd2 vdd3 c21 20p vdd3 mdc vdd3 rxclk vdd3 r28 4.7k rxd2 f1 fuse txd3 txd2 d6 1n4148 txd0 170ap2a.sch 2.0 ax88170 asix electronic corporation b 2 2 monday, february 26, 2001 title size document number rev date: sheet of txd0 crs vdd3 d5 led r23 4.7k eedo 48m_xin rst#
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 32 txd2 rxdv ring vdd3 txen r13 10k vdd3 c3 0.1u r14 49.9 txd3 txen r4 20 + c10 47u/16v txd0 tip 25mhz r6 10k 170ap2a1.sch 2.0 homenet phy c.k.t. b 1 2 monday, february 26, 2001 title size document number rev date: sheet of mdio txclk c8 0.01u col rxd0 vdd3 vdd3 powerled# txclk colled# powerled# r2 4.7k c14 0.1u c4 0.1u txclk r7 20 vdd3 crs rxd2 txd3 r15 49.9 u2 hr002 5 4 3 2 1 7 8 6 12 13 14 15 16 11 10 9 nc nc gnd - + nc nc nc nc nc nc nc nc nc tip ring rxd3 speedled# r8 330 + c1 47u/16v txd0 c7 0.01u rxclk rxd0 crs rxd3 col mdc actled# rxclk avdd3_1 r9 4.7k u1 dp83851c 36 35 34 33 32 31 23 24 25 26 27 28 37 38 21 22 45 46 19 29 39 5 11 20 7 8 4 17 18 16 15 44 14 42 43 48 30 40 41 47 3 6 10 1 2 9 12 13 txd3 txd2 txd1 txd0/txd tx_en tx_clk rxd3/phyad0 rxd2/cmddis# rxd1/hi_power_en# rxd0/rxd/low_speed_en# rx_dv/gpsi_sel# rx_clk col/mdio_int_en# crs/pin_intrp_en# mdio mdc x1 x2 io_vdd1 io_vdd2 core_vdd ana_vdd2 ana_vdd3 io_gnd1 tip ring rbias led_col/phyad2 led_act/phyad1 led_speed/phyad3 led_power/phyad4 reset# reserved reserved reserved ana_vdd1 io_gnd2 core_gnd core_sub(0v) ana_gnd1 ana_gnd2 ana_gnd3 ana_gnd4 sub_gnd1 sub_gnd2 sub_gnd3 reserved reserved d3 yellow led txd3 avdd3_2 txd1 r11 330 d1 green led r17 0 speedled# txen rxclk mdc gnd r16 4.7k prst# mdc crs d2 yellow led r3 10k gnd rxd3 vdd3 l1 f.b. c13 0.01u j1 rj11 1 2 3 4 5 6 nc a1 tip ring a2 nc rxd1 + c5 47u/16v rxd1 c12 0.01u rxd1 actled# txd2 vdd3 25mhz txd0 col txd1 + c6 47u/16v 25mhz r5 330 + c11 47u/16v mdio d4 red led mdio vdd3 rxdv prst# r12 9.31k 1% c2 0.01u tip c9 0.1u rxd2 r1 330 l2 f.b. rxd2 txd2 txd1 rxdv r10 10k set phy address to 00001 and led display c.k.t. ?g prst# rxd0 colled# ring vdd3
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 33 demonstration circuit c: 4 us b ports + 1 ethernet port bridge ap u4c 74hc04 5 6 (power in: 5v/3a) c12 0.1u 25m_phy rst_usb# 25m_usb1 u5 osc 25mhz 5 4 8 out gnd vcc gnd + c1 200u/16v rst_usb# 25m_usb0 *2 r9 & r10 : adjust dm9191f lclk to ax88875ap lclk c5 1000p l3 f.b. vdd5 25m_usb3 vdd5 25mhz 25m_usb3 c7 1000p u4a 74hc04 1 2 u2d 74lv04 9 8 gnd l2 f.b. ax88170 l phy mode application (mii interface) u2a 74lv04 1 2 r5 20 25m_phy u2c 74lv04 5 6 l1 f.b. gnd5 r3 20 25m_usb2 vdd5 25m_usb0 vdd5 vdd3 u6c 74f04 5 6 rst_en# r10 20 c11 0.1u jp1 power connector 4 3 2 1 vdd3 r6 20 c9 0.1u u1 ams1084-3.3v 3 2 1 vin vout adj/gnd rst_en# u2b 74lv04 3 4 r4 51 vdd5 25m_usb2 r2 20 u4b 74hc04 3 4 *1 r7 & r8 : adjust ax88875ap lclk to ax88170 l txclk 25m_usb1 r1 10k gnd rst_en# + c3 47u/16v u3 v6300f 1 2 3 vcc reset# gnd r9 20 vdd5 + c2 200u/16v vdd5 25m_rep 25m_rep u2e 74lv04 11 10 25m_usb0 c4 0.1u 25m_usb2 + c8 47u/16v 25m_usb1 c6 0.1u r7 20 u6a 74f04 1 2 25m_usb3 rst_usb# vdd3 vdd3 c13 1000p c10 0.01u +5v gnd r8 20 gnd 170ap5a.sch 2.0 power & reset c.k.t. b 1 7 monday, february 26, 2001 title size document number rev date: sheet of 25m_rep 25m_phy u6b 74f04 3 4
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 34 r18 10k rxd03 txd0 txd00 y1 48m d- vdd3 aldone 170ap5a1.sch 2.0 ax88170 circuit 1 asix electronic corporation b 2 7 monday, february 26, 2001 title size document number rev date: sheet of c23 8p d1 led gnd 48m_xout r12 330 txd02 gnd 1 2 4 3 j1 usb-con 1 2 3 4 gnd vdd5 d+ d- s s txd1 rxd2 *3 usb port link/act led rxd1 rst# r13 1.5k vdd3 r16 4.7k r15 18 eecs txen eedo c21 0.1u vdd3 48m_xin c15 20p rxd02 c16 0.01u txd01 c24 22pf vdd3 rxdv0 vdd3 l4 f.b. vdd3 txen0 u8 93c56r 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc rst_usb# c19 0.1u vdd3 c22 8p q1 2sc2412k u7 ax88170 l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d+ d- vdd /rst vss spd_up s_ext /s_fdpx /s_mac vdd vss mdc col mdio crs tx_clk vss txd0 txd1 txd2 txd3 tx_en vdd rx_clk vss rxd0 rxd1 rxd2 rxd3 vdd rx_er rx_dv 25m_clko vss 25m_xin 25m_xout vdd gpio0 /phy_rst gpio1 /homelink vss /s_rmii vdd eecs eeck eedi eedo vss vdd 48m_xout 48m_xin vss vdd test0 test1 test2 /ep78dis test3 vdd test_out test4 leerdy act/link vss txd2 txd3 r14 18 vdd3 txd03 rxd00 eedo c18 0.1u 48m_xin rxclk r11 1k l5 2.2uh r20 0 vdd3 rxd01 crs0 vdd3 d+ vdd3 rxdv c17 0.1u act/link# 25m_usb0 vdd3 crs r19 10k eeck rxd0 c14 20p r17 20k eecs c20 0.1u eedi eeck rxd3 48m_xout rxclk0 eedi
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 35 l6 f.b. 170ap5a2.sch 2.0 ax88170 circuit 2 asix electronic corporation b 3 7 monday, february 26, 2001 title size document number rev date: sheet of eedi rst# txen r30 0 act/link# rxd1 c35 22pf rxd3 48m_xout rxd0 rxd2 *4 usb port link/act led rxclk1 rxdv1 eeck gnd vdd3 vdd3 d+ rxdv vdd3 vdd3 y2 48m 48m_xin aldone rxclk 48m_xin d2 led crs1 c29 0.1u r26 4.7k c26 20p c28 0.1u c34 8p eecs crs rst_usb# txd12 vdd3 rxd11 txd1 vdd3 vdd3 eedo txen1 l7 2.2uh r23 1.5k vdd3 c30 0.1u c31 0.1u c33 8p vdd3 r27 20k txd0 eedi 48m_xout c27 0.01u c25 20p vdd3 eeck r29 10k r22 330 rxd13 txd2 1 2 4 3 j2 usb-con 1 2 3 4 gnd vdd5 d+ d- s s u10 93c56r 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc q2 2sc2412k txd3 d- u9 ax88170 l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d+ d- vdd /rst vss spd_up s_ext /s_fdpx /s_mac vdd vss mdc col mdio crs tx_clk vss txd0 txd1 txd2 txd3 tx_en vdd rx_clk vss rxd0 rxd1 rxd2 rxd3 vdd rx_er rx_dv 25m_clko vss 25m_xin 25m_xout vdd gpio0 /phy_rst gpio1 /homelink vss /s_rmii vdd eecs eeck eedi eedo vss vdd 48m_xout 48m_xin vss vdd test0 test1 test2 /ep78dis test3 vdd test_out test4 leerdy act/link vss c32 0.1u vdd3 r28 10k 25m_usb1 eecs r21 1k txd10 vdd3 rxd10 txd11 rxd12 r24 18 r25 18 txd13 gnd eedo
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 36 vdd3 48m_xin r35 18 r36 4.7k rxclk u11 ax88170 l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d+ d- vdd /rst vss spd_up s_ext /s_fdpx /s_mac vdd vss mdc col mdio crs tx_clk vss txd0 txd1 txd2 txd3 tx_en vdd rx_clk vss rxd0 rxd1 rxd2 rxd3 vdd rx_er rx_dv 25m_clko vss 25m_xin 25m_xout vdd gpio0 /phy_rst gpio1 /homelink vss /s_rmii vdd eecs eeck eedi eedo vss vdd 48m_xout 48m_xin vss vdd test0 test1 test2 /ep78dis test3 vdd test_out test4 leerdy act/link vss vdd3 rst# 170ap5a3.sch 2.0 ax88170 circuit 3 asix electronic corporation b 4 7 monday, february 26, 2001 title size document number rev date: sheet of vdd3 gnd 48m_xin txd3 act/link# rxclk2 eecs vdd3 c40 0.1u vdd3 r33 1.5k 1 2 4 3 j3 usb-con 1 2 3 4 gnd vdd5 d+ d- s s rxd0 txd2 aldone rst_usb# c42 0.1u eedo u12 93c56r 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc eeck rxdv2 eedi c44 8p r38 10k txd21 d- 48m_xout vdd3 txd0 crs2 vdd3 r32 330 eeck crs txd23 r40 0 r31 1k y3 48m rxd2 c43 0.1u c41 0.1u l9 2.2uh txen eedo d+ vdd3 vdd3 c37 20p vdd3 rxd1 rxdv rxd20 r39 10k rxd3 r34 18 rxd21 *5 usb port link/act led c36 20p r37 20k l8 f.b. gnd txd1 vdd3 eedi txen2 rxd23 48m_xout txd20 rxd22 d3 led eecs 25m_usb2 c39 0.1u q3 2sc2412k vdd3 c46 22pf txd22 c45 8p c38 0.01u
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 37 rxdv3 rxd0 txd0 vdd3 r46 4.7k vdd3 txd1 rxd33 txd2 r49 10k eecs crs3 c52 0.1u l10 f.b. r41 1k txd33 eecs eeck c55 8p eedo txd32 rxdv 25m_usb3 d4 led rst_usb# txd31 r44 18 vdd3 rst# rxd30 txen 48m_xout c57 22pf c50 0.1u r48 10k d- rxd31 rxd1 vdd3 r43 1.5k u13 ax88170 l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d+ d- vdd /rst vss spd_up s_ext /s_fdpx /s_mac vdd vss mdc col mdio crs tx_clk vss txd0 txd1 txd2 txd3 tx_en vdd rx_clk vss rxd0 rxd1 rxd2 rxd3 vdd rx_er rx_dv 25m_clko vss 25m_xin 25m_xout vdd gpio0 /phy_rst gpio1 /homelink vss /s_rmii vdd eecs eeck eedi eedo vss vdd 48m_xout 48m_xin vss vdd test0 test1 test2 /ep78dis test3 vdd test_out test4 leerdy act/link vss vdd3 y4 48m c48 20p c51 0.1u rxd3 c49 0.01u crs c47 20p r45 18 vdd3 c56 8p vdd3 d+ txd3 rxd32 *6 usb port link/act led txd30 aldone l11 2.2uh gnd vdd3 vdd3 rxd2 vdd3 rxclk r42 330 48m_xin act/link# 48m_xin 170ap5a4.sch 2.0 ax88170 circuit 4 asix electronic corporation b 5 7 monday, february 26, 2001 title size document number rev date: sheet of 1 2 4 3 j4 usb-con 1 2 3 4 gnd vdd5 d+ d- s s rxclk3 vdd3 r47 20k 48m_xout eedo c53 0.1u eedi q4 2sc2412k eedi r50 0 vdd3 eeck gnd txen3 u14 93c56r 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc c54 0.1u
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 38 rxclk4 r59 10k txen1 mode0 rxdv1 md3 c60 0.1u txd02 vdd5 r66 20 r51 20 c70 0.1u mems1 md0 c63 0.1u rxclk1 rxd21 ma11 gnd col10# rxd01 ma7 r71 510 rxd10 rxdv3 txd32 crs3 disfc# txd30 + c58 100u/16v txd13 *10 settingt to mode 0 ma0 gnd vdd5 ma6 txer4 d6 led r67 10k r56 10k r57 10k gnd disfc# txd03 txd01 txd31 gnd rxd22 vdd5 txd42 ma0 col100# md7 md2 md3 gnd ma16 r53 10k rxd43 rxd03 vdd5 txd10 ma16 gnd rxclk0 rxd12 vdd5 r72 10k md1 vdd5 st_fw ma11 u16 hsram128*8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 n.c. a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 cs2 we_# a13 a8 a9 a11 oe_# a10 cs1_# i/o8 i/o7 i/o6 i/o5 i/o4 gnd md4 c61 0.1u txd20 rxdv0 rxd41 rxd00 ma1 col100# rxd20 r52 10k c66 0.1u vdd5 vdd5 txd33 lled4 gnd txd40 txd43 ma3 *9 low: dis_flow-control txd23 crs0 100 global collision gnd md2 md6 mode0 lclk r65 10k entry gnd rst# txen0 gnd txd21 txen3 rxd23 ma14 vdd5 rxd33 entry rxd40 rxd42 mwr# c65 0.1u r60 20 r62 10k vdd5 gnd c67 0.1u ma15 ma14 10 global collision ma7 ma5 vdd5 u15 ax88875ap 1 2 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 vdd rxd<1><2> txd<3><1> txd<3><2> txd<3><3> txer3<3> col<3> vss pull_dn en_flow-ctl mode txe_delay vdd rxer<4> rxdv<4> crs<4> vss vdd rxclk<4> rxd<4><0> rxd<4><1> rxd<4><2> rxd<4><3> txen<4> txd<4><0> mem_size<0> txd<4><1> mem_size<1> txd<4><2> entries txd<4><3> st_fw txer<4> col<4> col_o<4> vss /lcol100 mdc mdo mclk /bma<15> /luti<0> /luti<1> /luti<2> /luti<3> /bmwr /ir_act_en bma<8> bma<9> /lpart<4> vss /lact<4> nc /lact<2> /lact<3> vdd nc /lact<0> /lact<1> nc test1 /rst vss lclk /half10 vdd pull_dn pull_dn vdd vss rxer<0> rxdv<0> crs<0> rxclk<0> rxd<0><0> rxd<0><1> rxd<0><2> rxd<0><3> vss txen<0> txd<0><0> txd<0><1> txd<0><2> txd<0><3> col<0> txer<0> rxer<1> rxdv<1> crs<1> rxclk<1> rxd<1><0> rxd<1><1> rxd<1><3> txen<1> txd<1><0> txd<1><1> txd<1><2> txd<1><3> txer<1> col<1> vss pull_dn pull_dn vdd vss rxer<2> rxdv<2> crs<2> rxclk<2> rxd<2><0> rxd<2><1> rxd<2><2> rxd<2><3> txen<2> txd<2><0> txd<2><1> txd<2><2> txd<2><3> txer<2> col<2> vss rxer<3> rxdv<3> crs<3> rxclk<3> rxd<3><0> rxd<3><1> rxd<3><2> rxd<3><3> vdd txen<3> txd<3><0> vdd bma<10> bma<11> bma<12> bma<13> bma<14> bma<15> bma<16> vss bmd<0> bmd<1> bmd<2> bmd<3> bmd<4> bmd<5> bmd<6> bmd<7> vss bma<0> bma<1> bma<2> bma<3> vdd bma<4> bma<5> bma<6> bma<7> vss vdd /lsel10 /lcol10 /luti<5> /luti<4> /test2 /lpart<0> /lpart<1> /lpart<2> lpart<3> txd22 md6 vdd5 txd00 25m_rep ma13 ma3 ma9 c69 0.1u rxclk2 md0 ma4 mwr# d5 led r54 10k gnd rxdv2 md1 r58 10k rxclk3 col10# gnd gnd *7 set memory size to 128kb ma2 ma10 ma1 ma12 crs1 md7 ma8 r55 10k crs2 rxd32 170ap5a5.sch 2.0 ax88875 ap c.k.t. b 6 7 monday, february 26, 2001 title size document number rev date: sheet of md5 vdd5 gnd rxd31 rxdv4 *8 entries setting : high : 256 low : 1024 r68 10k gnd md4 r64 10k ma8 ma9 ma10 c68 0.1u ma15 c62 0.1u c71 0.1u ma13 ma4 r69 510 r61 20 r70 20 c64 0.1u ma6 mems1 c59 0.1u txd11 txd12 rxd13 rst_en# mems0 vdd5 ma2 rxd11 rxd02 rxd30 md5 r63 10k ma5 txen2 txen4 crs4 rxer4 gnd ma12 txd41
ax88170 usb to fast ethernet /homepna controller asix electronics corporation 39 rxd0 lled c92 0.1u c81 0.1u txer c79 1000p c91 0.1u agnd txd43 tdn r75 49.9 l12 f.b. gnd crs c83 0.1u rxd41 rj03 c82 0.1u rj03 rxclk gnd c87 0.1u txd1 c74 0.1u txer vdd5 gnd rxer gnd rxd43 avdd5 r79 75 crs4 rdp rdn c73 0.01u/2kv avdd5 gnd rxd1 agnd 170ap5a6.sch 2.0 ethernet phy c.k.t. b 7 7 monday, february 26, 2001 title size document number rev date: sheet of txd0 tdp txd2 txd3 gnd r74 49.9 agnd rxdv4 crs avdd5 c78 1000p txd2 gnd rxer4 rxd2 gnd vdd5 + c86 47u/16v agnd vdd5 avdd5 gnd c76 0.01u r80 75 r73 49.9 chassis jp3 rj45 1 2 3 4 5 6 7 8 rxd0 vdd5 u17 dm9191f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 avcc nc nc nc nc agnd avcc avcc rxi- rxi+ agnd agnd 10txo- 10txo+ avcc avcc agnd agnd nc nc avcc avcc agnd agnd 100txo- 100txo+ avcc dvcc osc/x1 x2 dgnd osc/xlt# avcc agnd bgres nc dgnd dgnd agnd avcc tridrv utp speed10 rx_lock dgnd nc linksts clk25m dvcc fdxled# colled# dgnd linkled# rxled# txled# tx_er/txd4 txd3 txd2 txd1 txd0 dgnd dvcc tx_en tx_clk mdc mdio dgnd dvcc rxd3 rxd2 rxd1 rxd0 dgnd dvcc rx_clk crs col rx_dv rx_er/rxd4 rx_en reset# testdome phyad0 phyad1 phyad2 dgnd dvcc phyad3 phyad4 opmode0 opmode1 opmode2 opmode3 rptr/node# bpalign bp4b5b bpscr 10btser agnd agnd rj02 (ethernet port) vdd5 c84 0.1u c80 0.1u rst# jp2 rj45 1 2 3 4 5 6 7 8 gnd_e vdd5 + c77 47u/16v tdp rdp ethernet port link/act led vdd5 vdd5 c93 0.1u rj06 gnd tdp rst_en# agnd vdd5 txd3 txd40 avdd5 agnd txd41 tx 1ct:1ct rx 1ct:1ct rj02 rj01 rj03 rst# rxd1 25m_phy agnd txen (1%) gnd rdn c90 0.1u r82 510 vdd5 gnd vdd5 vdd5 vdd5 gnd rxd2 vdd5 lled4 rj06 rxd40 agnd txen rxclk avdd5 rj06 r78 75 c85 0.1u (ethernet uplink poart) avdd5 c72 0.1u vdd5 rxer t1 16st8515 16 14 15 1 3 2 10 12 11 7 5 6 16 14 15 1 3 2 10 12 11 7 5 6 rxd42 txen4 rj02 avdd5 lled4 d7 green led c89 0.1u 25m_phy tdn txer4 25m_phy gnd r81 6.2k txd0 avdd5 c75 0.1u rxd3 vdd5 c88 0.1u gnd r76 49.9 rxclk4 r77 75 rxdv gnd lled4 tdn agnd txd42 txd1 rj01 vdd5 gnd rxdv rj01 rxd3

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